For typical Flash EPROM (erasable programmable read only memory) formation, a self-aligned-source (SAS) etch process is used. An example of a SAS process includes U.S. Pat. No. 5,120,671, entitled "Process for Self Aligning a Source Region with a Field Oxide Region and a Polysilicon Gate". With the SAS etch process, a field oxide of the EPROM cell is etched away and a source line is formed that is self-aligned to the stacked gate of the EPROM cell and eliminates the need for an overlap of the field oxide area of the stacked gate. By using this process, the stacked gates are suitably formed close together resulting in a significant reduction in core cell area. Further, with the reduction in core cell area, the density of Flash EPROM cells is increased, thus making the SAS etch process a mainstay in nearly all current Flash EPROM cell formation processes.
Unfortunately, the SAS etch process also potentially affects the integrity of the silicon substrate of the cell. The selectivity in etch rates between the silicon of the substrate and the field oxide largely determines the amount of silicon unintentionally etched during the SAS etch process. Some of the undesirable effects or negative impacts of such gouging in the silicon substrate on the core cell array characteristics include poor erase distribution, slow erase speed, higher column leakage, and more erratic bits. Hence, it is considered highly important to monitor the gouging. Heretofore, attempts to monitor gouging have typically used destructive techniques, such as SEM or TEM cross-sectional methods.
What is needed is a test method used to determine the amount of gouging that occurs during SAS etch and that can be incorporated into the typical, electrical, wafer level testing routines.